1. Field of the Invention
The present invention relates to a semiconductor circuit including a digital logic circuit and a scan path circuit for performing test and fault analysis of a digital logic circuit using the scan path circuit.
2. Description of the Related
A scan path circuit is installed and used in a semiconductor circuit for the purpose of facilitating preparation of test patterns for production shipment tests of digital logic circuits and facilitating fault analysis of logic circuits. A scan path circuit makes it possible to handle a complex circuit by separating it into flip-flops and combination circuits and to facilitate circuit tests, fault analysis, etc., therefore is currently widely used in LSIs (large-scale integrated circuits) having complex processing and computation functions and including a large scale sequential circuit.
FIG. 1 is a view of an example of a semiconductor circuit including a scan path circuit. As shown in the figure, the semiconductor circuit comprises a combinational circuit C81 and scan path circuits F81 and F82.
The combination circuit C81 performs a predetermined digital signal processing and logical operation in accordance with input data N.sub.in and outputs a processing result N.sub.out.
The scan path circuits F81 and F82 are respectively comprised of a plurality of flip-flops. The flip-flops are controlled by a commonly input scan path enable signal SE and a clock signal CK.
The scan path circuit F81 successively shifts input data S.sub.in1 to an output side and outputs an output signal S.sub.out1. A test pattern is formed by the scan path circuit F81 in accordance with the input data S.sub.in1 for testing an operation of the combinational circuit C81, data of each bit of the test pattern, that is, held data of each flip-flop comprising the scan path circuit F81, is transferred to the combinational circuit C81, and the processing result of the combinational circuit C81 is transferred to the scan path circuit F81 and successively output to the output side by the scan path circuit F81. The scan path circuit F82 operates in the substantially the same way as the scan path circuit F81. Note that the number of scan path circuits provided in the combinational circuit C81 is two in this example, but only one or a plurality of scan path circuits can also be provided.
As explained above, the scan path circuits F81 and F82 are provided other than the combinational circuit C81 having a function of predetermined processing in the semiconductor circuit, and a test pattern is formed by the scan path circuits and supplied to the combinational circuit C81, or a processing result of the combinational circuit C81 is fetched and successively output as serial data. Therefore, a function test and fault analysis etc. of the combinational circuit C81 conducted before shipment become easy and a test and analysis of an LSI having a complex processing function can be efficiently conducted.
In the above conventional semiconductor circuit, it is easy to perform reverse engineering by using a scan path circuit. Reverse engineering means to find the configuration of a logic circuit inside an LSI based on a real LSI or a simulation model. This is liable to lead to violation of intellectual property such as copying others' products. For example, in an LSI using a scan path circuit, any values can be set in a flip-flops and the values of the flip-flops can be freely read, so it is easy to guess how the combinational circuit is configured and how it functions by the input/output data of the flip-flops. Accordingly, the disadvantage arises that manufacturers producing semiconductor circuits have to take steps to prevent reverse engineering such as stopping using scan path circuits or relying on built-in self-tests (BIST) etc.
FIG. 2 is a view of an example of a semiconductor circuit having a built-in self-test function. As shown in the figure, the semiconductor circuit comprises a combinational circuit C91, a pseudo random number generating circuit B91, a data compression circuit B92, and scan path circuits F91 and F92. Here, the combinational circuit C91 and the scan path circuits F91 and F92 are substantially the same as the respective circuits of the semiconductor circuit shown in FIG. 1. The pseudo random number generating circuit B91 and the data compression circuit B92 will be explained below.
The pseudo random number generating circuit B91 generates a pseudo random number string in accordance with input signals S.sub.in1 and S.sub.in2 and inputs the generated pseudo random number string to the scan path circuits F91 and F92. FIG. 3 shows an example of the configuration of the pseudo random number generating circuit B91. As shown in the figure, the pseudo random number generating circuit B91 comprises n number (n is a natural number) of flip-flops connected in series and a logic gate. An exclusive OR of output data of a predetermined flip-flop is fed back to the first flip-flop. A pseudo random number string having a period of (2.sup.n -1) is generated by the pseudo random number generating circuit B91 configured in this way. The data S.sub.in1 and S.sub.in2 input from the outside are input to the first and second flip-flops F101 and F102 via exclusive OR circuits XOR1 and XOR2, so an initial value of a pseudo random number string generated by the pseudo random number generating circuit B91 is set in accordance with the input data. Further, data B.sub.in1 and B.sub.in2 are output from the output terminals of the exclusive OR circuits XOR1 and XOR2 and respectively supplied to scan path circuits F91 and F92.
The scan path circuits F91 and F92 are configured by a plurality of flip-flops connected in series, respectively, in substantially the same way as in the scan path circuits F81 and F82 in the semiconductor circuit in FIG. 1. The input data is successively shifted to the output side by the scan path circuits. The data B.sub.in1 and B.sub.in2 input from the pseudo random number generating circuit B91 are successively shifted by the scan path circuits F91 and F92 to form a test pattern. Then, the test pattern formed in the scan path circuit F91 or F92 is transferred to the combinational circuit C91, a predetermined processing is performed in accordance with the input test pattern in the combinational circuit C91, and the processing result is transferred to the scan path circuits F91 and F92.
The data compression circuit B92 compresses data input from the scan path circuits F91 and F92 and outputs compressed data strings B.sub.out1 and B.sub.out2.
As a result, it becomes impossible to set any value to the combinational circuit C91 via the scan paths circuits F91 and F92 or to freely read data from the scan path circuits F91 and F92, so reverse engineering becomes difficult.
A semiconductor circuit having the above built-in self-test function, however, has the following disadvantages. First, since the test data string input to the combinational circuit is a pseudo random pattern generated from a pseudo random number string, the fault detection rate is low in many cases. Next, since the output response data string is output compressed by the data compression circuit, it is difficult to guess the faulty part even if detecting a fault.
Furthermore, tests of the peripheral circuits around the core cell are difficult. Advances in processes for miniaturization of LSIs have led to frequent design of new LSIs by using former LSIs as existing blocks, called "core cells", and combining the core cells. When using a built-in self-test circuit, since the signal input to the core cell is ignored, it cannot be used for testing core cell peripheral circuits. It is possible to provide a scan path mode in the built-in self-test circuit and test core cell peripheral circuits by this scan path mode, but this cannot be used in view of the need to prevent reverse engineering.